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- Kim, Jingook
- Integrated Circuit and Electromagnetic Compatibility Lab.
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Jitter-Aware Target Impedance
- Author(s)
- Sun, Yin, Kim, Jingook, Hwang, Chulsoon
- Issued Date
- 2019-07-22
- Citation
- 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, EMC+SIPI 2019, pp.217 - 222
- Abstract
- A new concept of target impedance which directly correlates the I/O buffer output jitter with the power distribution network (PDN) design is proposed. Jitter-ware target impedance is derived from the time domain waveform of power voltage ripple and the maximum allowable jitter assuming the single stage buffer as a RC network, which is then applied to the PDN design given a certain jitter specification. From HSPICE simulation of transient switching current, PDN impedance and power voltage ripple, it is shown that the proposed jitter-aware target impedance successfully correlates power supply induced jitter (PSIJ) and PDN impedance parameters with a simple analytical expression.
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- ISSN
- 0000-0000
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