dc.citation.conferencePlace |
US |
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dc.citation.conferencePlace |
New Orleans |
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dc.citation.endPage |
222 |
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dc.citation.startPage |
217 |
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dc.citation.title |
2019 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, EMC+SIPI 2019 |
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dc.contributor.author |
Sun, Yin |
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dc.contributor.author |
Kim, Jingook |
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dc.contributor.author |
Hwang, Chulsoon |
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dc.date.accessioned |
2024-02-01T00:06:35Z |
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dc.date.available |
2024-02-01T00:06:35Z |
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dc.date.created |
2019-10-25 |
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dc.date.issued |
2019-07-22 |
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dc.description.abstract |
A new concept of target impedance which directly correlates the I/O buffer output jitter with the power distribution network (PDN) design is proposed. Jitter-ware target impedance is derived from the time domain waveform of power voltage ripple and the maximum allowable jitter assuming the single stage buffer as a RC network, which is then applied to the PDN design given a certain jitter specification. From HSPICE simulation of transient switching current, PDN impedance and power voltage ripple, it is shown that the proposed jitter-aware target impedance successfully correlates power supply induced jitter (PSIJ) and PDN impedance parameters with a simple analytical expression. |
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dc.identifier.bibliographicCitation |
2019 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, EMC+SIPI 2019, pp.217 - 222 |
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dc.identifier.doi |
10.1109/ISEMC.2019.8825313 |
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dc.identifier.issn |
0000-0000 |
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dc.identifier.scopusid |
2-s2.0-85073064844 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/79472 |
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dc.identifier.url |
https://ieeexplore.ieee.org/document/8825313 |
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dc.language |
영어 |
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dc.publisher |
Institute of Electrical and Electronics Engineers Inc. |
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dc.title |
Jitter-Aware Target Impedance |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2019-07-22 |
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