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Kim, Kyung Rok
Nano-Electronic Emerging Devices Lab.
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Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Author(s)
Kim, DHSung, SKKim, Kyung RokLee, JDPark, BGChoi, BHHwang, SWAhn, D
Issued Date
2002-04
URI
https://scholarworks.unist.ac.kr/handle/201301/7943
Fulltext
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=0036539033
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v.49, no.4, pp.627 - 635
Abstract
Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
0018-9383

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