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Kim, Kyung Rok
Nano-Electronic Emerging Devices (NEEDs) Lab
Research Interests
  • Nano-CMOS, neuromorphic device, terahertz (THz) plasma-wave transistor (PWT)

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Single-electron transistors fabricated with sidewall spacer patterning

Cited 7 times inthomson ciCited 7 times inthomson ci
Title
Single-electron transistors fabricated with sidewall spacer patterning
Author
Park, BGKim, DHKim, Kyung RokSong, KWLee, JD
Keywords
Complementary self-biasing method; DGSET; MOSET; Multi-valued logic; Phase control; Sidewall depletion gate; Sidewall spacer patterning; Single-electron transistor; SPICE
Issue Date
2003-09
Publisher
ACADEMIC PRESS LTD- ELSEVIER SCIENCE LTD
Citation
SUPERLATTICES AND MICROSTRUCTURES, v.34, no.3-6, pp.231 - 239
Abstract
We have implemented a sidewall spacer patterning method for novel dual-gate single-electron transistor (DGSET) and metal-oxide-semiconductor-based SET (MOSET) based on the uniform SOI wire, using conventional lithography and processing technology. A 30 nm wide silicon quantum wire is defined by a sidewall spacer patterning method, and depletion gates for two tunnel junctions of the DGSET are formed by the doped polycrystalline silicon sidewall. The fabricated DGSET and MOSET show clear single-electron tunneling phenomena at liquid nitrogen temperature and insensitivity of the Coulomb oscillation period to gate bias conditions. On the basis of the phase control capability of the sidewall depletion gates, we have proposed a complementary self-biasing method, which enables the SET/CMOS hybrid multi-valued logic (MVL) to operate perfectly well at high temperature, where the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical DGSET model, and it is confirmed that even DGSETs with a large Si island can be utilized efficiently in the multi-valued logic.
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DOI
10.1016/j.spmi.2004.03.013
ISSN
0749-6036
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