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Kim, Kyung Rok
Nano-Electronic Emerging Devices (NEEDs) Lab
Research Interests
  • Nano-CMOS, neuromorphic device, terahertz (THz) plasma-wave transistor (PWT)

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Single-electron transistors fabricated with sidewall spacer patterning

DC Field Value Language
dc.contributor.author Park, BG ko
dc.contributor.author Kim, DH ko
dc.contributor.author Kim, Kyung Rok ko
dc.contributor.author Song, KW ko
dc.contributor.author Lee, JD ko
dc.date.available 2014-10-29T00:21:25Z -
dc.date.created 2014-10-28 ko
dc.date.issued 2003-09 -
dc.identifier.citation SUPERLATTICES AND MICROSTRUCTURES, v.34, no.3-6, pp.231 - 239 ko
dc.identifier.issn 0749-6036 ko
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/7923 -
dc.identifier.uri http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=3242685133 ko
dc.description.abstract We have implemented a sidewall spacer patterning method for novel dual-gate single-electron transistor (DGSET) and metal-oxide-semiconductor-based SET (MOSET) based on the uniform SOI wire, using conventional lithography and processing technology. A 30 nm wide silicon quantum wire is defined by a sidewall spacer patterning method, and depletion gates for two tunnel junctions of the DGSET are formed by the doped polycrystalline silicon sidewall. The fabricated DGSET and MOSET show clear single-electron tunneling phenomena at liquid nitrogen temperature and insensitivity of the Coulomb oscillation period to gate bias conditions. On the basis of the phase control capability of the sidewall depletion gates, we have proposed a complementary self-biasing method, which enables the SET/CMOS hybrid multi-valued logic (MVL) to operate perfectly well at high temperature, where the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical DGSET model, and it is confirmed that even DGSETs with a large Si island can be utilized efficiently in the multi-valued logic. ko
dc.description.statementofresponsibility close -
dc.language ENG ko
dc.publisher ACADEMIC PRESS LTD- ELSEVIER SCIENCE LTD ko
dc.subject Complementary self-biasing method ko
dc.subject DGSET ko
dc.subject MOSET ko
dc.subject Multi-valued logic ko
dc.subject Phase control ko
dc.subject Sidewall depletion gate ko
dc.subject Sidewall spacer patterning ko
dc.subject Single-electron transistor ko
dc.subject SPICE ko
dc.title Single-electron transistors fabricated with sidewall spacer patterning ko
dc.type ARTICLE ko
dc.identifier.scopusid 2-s2.0-3242685133 ko
dc.identifier.wosid 000223571600016 ko
dc.type.rims ART ko
dc.description.wostc 7 *
dc.description.scopustc 7 *
dc.date.tcdate 2015-05-06 *
dc.date.scptcdate 2014-10-28 *
dc.identifier.doi 10.1016/j.spmi.2004.03.013 ko
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