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Kim, Kyung Rok
Nano-Electronic Emerging Devices (NEEDs) Lab
Research Interests
  • Nano-CMOS, neuromorphic device, terahertz (THz) plasma-wave transistor (PWT)

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Complementary self-biased logics based on single-electron transistor (SET)/CMOS hybrid process

Cited 3 times inthomson ciCited 3 times inthomson ci
Title
Complementary self-biased logics based on single-electron transistor (SET)/CMOS hybrid process
Author
Song, KWLee, YKSim, JSKim, Kyung RokLee, JDPark, BGYou, YSPark, JOJin, YSKim, YW
Issue Date
2005-04
Publisher
JAPAN SOC APPLIED PHYSICS
Citation
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEFCOMMUNICATIONS & REVIEW PAPERS, v.44, no.4B, pp.2618 - 2622
Abstract
We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100mV period and the CMOS transistors show a high voltage gain
URI
https://scholarworks.unist.ac.kr/handle/201301/7907
URL
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=21244493578
DOI
10.1143/JJAP.44.2618
ISSN
0021-4922
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