Complementary self-biased logics based on single-electron transistor (SET)/CMOS hybrid process
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- Complementary self-biased logics based on single-electron transistor (SET)/CMOS hybrid process
- Song, KW; Lee, YK; Sim, JS; Kim, Kyung Rok; Lee, JD; Park, BG; You, YS; Park, JO; Jin, YS; Kim, YW
- Issue Date
- JAPAN SOC APPLIED PHYSICS
- JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEFCOMMUNICATIONS & REVIEW PAPERS, v.44, no.4B, pp.2618 - 2622
- We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100mV period and the CMOS transistors show a high voltage gain
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