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DC Field | Value | Language |
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dc.citation.endPage | 2622 | - |
dc.citation.number | 4B | - |
dc.citation.startPage | 2618 | - |
dc.citation.title | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEFCOMMUNICATIONS & REVIEW PAPERS | - |
dc.citation.volume | 44 | - |
dc.contributor.author | Song, KW | - |
dc.contributor.author | Lee, YK | - |
dc.contributor.author | Sim, JS | - |
dc.contributor.author | Kim, Kyung Rok | - |
dc.contributor.author | Lee, JD | - |
dc.contributor.author | Park, BG | - |
dc.contributor.author | You, YS | - |
dc.contributor.author | Park, JO | - |
dc.contributor.author | Jin, YS | - |
dc.contributor.author | Kim, YW | - |
dc.date.accessioned | 2023-12-22T10:37:12Z | - |
dc.date.available | 2023-12-22T10:37:12Z | - |
dc.date.created | 2014-10-27 | - |
dc.date.issued | 2005-04 | - |
dc.description.abstract | We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100mV period and the CMOS transistors show a high voltage gain | - |
dc.identifier.bibliographicCitation | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEFCOMMUNICATIONS & REVIEW PAPERS, v.44, no.4B, pp.2618 - 2622 | - |
dc.identifier.doi | 10.1143/JJAP.44.2618 | - |
dc.identifier.issn | 0021-4922 | - |
dc.identifier.scopusid | 2-s2.0-21244493578 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/7907 | - |
dc.identifier.url | http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=21244493578 | - |
dc.identifier.wosid | 000229095700118 | - |
dc.language | 영어 | - |
dc.publisher | JAPAN SOC APPLIED PHYSICS | - |
dc.title | Complementary self-biased logics based on single-electron transistor (SET)/CMOS hybrid process | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | single electron transistor | - |
dc.subject.keywordAuthor | SET | - |
dc.subject.keywordAuthor | Coulomb | - |
dc.subject.keywordAuthor | tunnelling | - |
dc.subject.keywordAuthor | multi-valuedlogic | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordPlus | OXIDE-SEMICONDUCTOR TRANSISTORS | - |
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