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Kim, Kyung Rok
Nano-Electronic Emerging Devices (NEEDs) Lab
Research Interests
  • Nano-CMOS, neuromorphic device, terahertz (THz) plasma-wave transistor (PWT)

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Complementary self-biased logics based on single-electron transistor (SET)/CMOS hybrid process

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dc.contributor.author Song, KW ko
dc.contributor.author Lee, YK ko
dc.contributor.author Sim, JS ko
dc.contributor.author Kim, Kyung Rok ko
dc.contributor.author Lee, JD ko
dc.contributor.author Park, BG ko
dc.contributor.author You, YS ko
dc.contributor.author Park, JO ko
dc.contributor.author Jin, YS ko
dc.contributor.author Kim, YW ko
dc.date.available 2014-10-29T00:21:04Z -
dc.date.created 2014-10-27 ko
dc.date.issued 2005-04 ko
dc.identifier.citation JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEFCOMMUNICATIONS & REVIEW PAPERS, v.44, no.4B, pp.2618 - 2622 ko
dc.identifier.issn 0021-4922 ko
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/7907 -
dc.description.abstract We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100mV period and the CMOS transistors show a high voltage gain ko
dc.description.statementofresponsibility close -
dc.language 영어 ko
dc.publisher JAPAN SOC APPLIED PHYSICS ko
dc.title Complementary self-biased logics based on single-electron transistor (SET)/CMOS hybrid process ko
dc.type ARTICLE ko
dc.identifier.scopusid 2-s2.0-21244493578 ko
dc.identifier.wosid 000229095700118 ko
dc.type.rims ART ko
dc.description.wostc 3 *
dc.description.scopustc 3 *
dc.date.tcdate 2015-05-06 *
dc.date.scptcdate 2014-10-27 *
dc.identifier.doi 10.1143/JJAP.44.2618 ko
dc.identifier.url http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=21244493578 ko
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