Multi-Bit MIP(Memory-in-Pixel)-Based Pixel Circuit of CMOS Backplane for Micro-LED Display

Abstract

The Micro‐LED display is getting more attention in AR/MR (Augmented/Mixed Reality) applications. The display size of 0.5 to 0.7‐inch is preferred with 5,000 or higher PPI (Pixel Per Inch). Due to the pixel density and size, a CMOS (Complementary Metal‐Oxide‐Silicon) backplane is a preferred solution for driving the pixelized micro‐LEDs. This paper proposes a multi‐bit MIP‐based pixel circuit with PWM driving for a CMOS backplane in order to minimize power dissipation. it also provides an estimation of the minimum achievable pixel size based on the CMOS process node.