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| DC Field | Value | Language |
|---|---|---|
| dc.citation.conferencePlace | KO | - |
| dc.citation.title | SID 2020 Digest | - |
| dc.contributor.author | Seong, Jewoo | - |
| dc.contributor.author | Jang, Jinwoong | - |
| dc.contributor.author | Lee, Jaehoon | - |
| dc.contributor.author | Lee, Myunghee | - |
| dc.date.accessioned | 2024-01-31T23:08:29Z | - |
| dc.date.available | 2024-01-31T23:08:29Z | - |
| dc.date.created | 2020-03-13 | - |
| dc.date.issued | 2020-00 | - |
| dc.description.abstract | The Micro‐LED display is getting more attention in AR/MR (Augmented/Mixed Reality) applications. The display size of 0.5 to 0.7‐inch is preferred with 5,000 or higher PPI (Pixel Per Inch). Due to the pixel density and size, a CMOS (Complementary Metal‐Oxide‐Silicon) backplane is a preferred solution for driving the pixelized micro‐LEDs. This paper proposes a multi‐bit MIP‐based pixel circuit with PWM driving for a CMOS backplane in order to minimize power dissipation. it also provides an estimation of the minimum achievable pixel size based on the CMOS process node. | - |
| dc.identifier.bibliographicCitation | SID 2020 Digest | - |
| dc.identifier.doi | 10.1002/sdtp.13878 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/78648 | - |
| dc.publisher | Society for Information Display | - |
| dc.title | Multi-Bit MIP(Memory-in-Pixel)-Based Pixel Circuit of CMOS Backplane for Micro-LED Display | - |
| dc.type | Conference Paper | - |
| dc.date.conferenceDate | 2020 | - |
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