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Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion

Author(s)
Kim, YoungminPetranovic, D.Sylvester, D.
Issued Date
2009-08
DOI
10.1109/TVLSI.2009.2020392
URI
https://scholarworks.unist.ac.kr/handle/201301/7849
Fulltext
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=68549115189
Citation
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.17, no.8, pp.1166 - 1170
Abstract
In this paper, we analyze and model the impact of floating dummy fill on the signal capacitance considering various parameters including signal dimensions, dummy shape and dimensions. Intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has larger impact on the ground capacitance component. Based on this analysis, we propose simple capacitance models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider realistic cases with both signals and metal fill in adjacent layers, we apply a weighting function approach to the Cg model. We verify this model using benchmark circuits and find that total net capacitance with floating fill can be extracted within similar to 1% of field solver results on average with total extraction runtime reductions of up to 40%. When evaluating the incremental capacitance due to fill alone, average error of the models range from 2%-15% across benchmarks and fill-related runtime overhead is reduced by 60%-88%.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
1063-8210

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