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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 1170 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1166 | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 17 | - |
dc.contributor.author | Kim, Youngmin | - |
dc.contributor.author | Petranovic, D. | - |
dc.contributor.author | Sylvester, D. | - |
dc.date.accessioned | 2023-12-22T07:42:08Z | - |
dc.date.available | 2023-12-22T07:42:08Z | - |
dc.date.created | 2014-10-28 | - |
dc.date.issued | 2009-08 | - |
dc.description.abstract | In this paper, we analyze and model the impact of floating dummy fill on the signal capacitance considering various parameters including signal dimensions, dummy shape and dimensions. Intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has larger impact on the ground capacitance component. Based on this analysis, we propose simple capacitance models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider realistic cases with both signals and metal fill in adjacent layers, we apply a weighting function approach to the Cg model. We verify this model using benchmark circuits and find that total net capacitance with floating fill can be extracted within similar to 1% of field solver results on average with total extraction runtime reductions of up to 40%. When evaluating the incremental capacitance due to fill alone, average error of the models range from 2%-15% across benchmarks and fill-related runtime overhead is reduced by 60%-88%. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.17, no.8, pp.1166 - 1170 | - |
dc.identifier.doi | 10.1109/TVLSI.2009.2020392 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.scopusid | 2-s2.0-68549115189 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/7849 | - |
dc.identifier.url | http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=68549115189 | - |
dc.identifier.wosid | 000268282700020 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion | - |
dc.type | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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