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Kim, Youngmin
Nano-scale(system) Design & Automation Lab
Research Interests
  • Design & Technology Co-Optimization (DTCO)
  • Variability-Aware and Robust Design Methodologies
  • Design for Manufacturability/Variability (DFM/V)
  • Low-Power and High Performance Circuit Design
  • 3D IC with TSV

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Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion

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dc.contributor.author Kim, Youngmin ko
dc.contributor.author Petranovic, D. ko
dc.contributor.author Sylvester, D. ko
dc.date.available 2014-10-29T00:19:17Z -
dc.date.created 2014-10-28 ko
dc.date.issued 2009-08 -
dc.identifier.citation IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.17, no.8, pp.1166 - 1170 ko
dc.identifier.issn 1063-8210 ko
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/7849 -
dc.identifier.uri http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=68549115189 ko
dc.description.abstract In this paper, we analyze and model the impact of floating dummy fill on the signal capacitance considering various parameters including signal dimensions, dummy shape and dimensions. Intra-layer dummy has its greatest impact on coupling capacitance while inter-layer dummy has larger impact on the ground capacitance component. Based on this analysis, we propose simple capacitance models (Cc for intra-layer dummy and Cg for inter-layer dummy). To consider realistic cases with both signals and metal fill in adjacent layers, we apply a weighting function approach to the Cg model. We verify this model using benchmark circuits and find that total net capacitance with floating fill can be extracted within similar to 1% of field solver results on average with total extraction runtime reductions of up to 40%. When evaluating the incremental capacitance due to fill alone, average error of the models range from 2%-15% across benchmarks and fill-related runtime overhead is reduced by 60%-88%. ko
dc.description.statementofresponsibility close -
dc.language ENG ko
dc.publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC ko
dc.subject Capacitance ko
dc.subject Design ko
dc.subject Integrated circuits (ICs) ko
dc.subject Interconnects ko
dc.title Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion ko
dc.type ARTICLE ko
dc.identifier.scopusid 2-s2.0-68549115189 ko
dc.identifier.wosid 000268282700020 ko
dc.type.rims ART ko
dc.description.wostc 2 *
dc.description.scopustc 4 *
dc.date.tcdate 2015-05-06 *
dc.date.scptcdate 2014-10-28 *
dc.identifier.doi 10.1109/TVLSI.2009.2020392 ko
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