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- Jeong, Changwook
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Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications
- Author(s)
- Cho, H.-J., Oh, H.S., Nam, K.J., Kim, Y.H., Yeo, K.H., Kim, W.D., Chung, Y.S., Nam, Y.S., Kim, S.M., Kwon, W.H., Kang, M.J., Kim, I.R., Fukutome, H., Jeong, Changwook, Shin, H.J., Kim, Y.S., Kim, D.W., Park, S.H., Jeong, J.H., Kim, S.B., Ha, D.W., Park, J.H., Rhee, H.S., Hyun, S.J., Shin, D.S., Kim, D.H., Kim, H.Y., Maeda, S., Lee, K.H., Kim, M.C., Koh, Y.S., Yoon, B., Shin, K., Lee, N.I., Kangh, S.B., Hwang, K.H., Lee, J.H., Ku, J.-H., Nam, S.W., Jung, S.M., Kang, H.K., Yoon, J.S., Jung, E.S.
- Issued Date
- 2016-06-13
- Citation
- 36th IEEE Symposium on VLSI Technology
- Abstract
- 10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- ISSN
- 0743-1562
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