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DC Field | Value | Language |
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dc.citation.conferencePlace | US | - |
dc.citation.conferencePlace | Honolulu | - |
dc.citation.title | 36th IEEE Symposium on VLSI Technology | - |
dc.contributor.author | Cho, H.-J. | - |
dc.contributor.author | Oh, H.S. | - |
dc.contributor.author | Nam, K.J. | - |
dc.contributor.author | Kim, Y.H. | - |
dc.contributor.author | Yeo, K.H. | - |
dc.contributor.author | Kim, W.D. | - |
dc.contributor.author | Chung, Y.S. | - |
dc.contributor.author | Nam, Y.S. | - |
dc.contributor.author | Kim, S.M. | - |
dc.contributor.author | Kwon, W.H. | - |
dc.contributor.author | Kang, M.J. | - |
dc.contributor.author | Kim, I.R. | - |
dc.contributor.author | Fukutome, H. | - |
dc.contributor.author | Jeong, Changwook | - |
dc.contributor.author | Shin, H.J. | - |
dc.contributor.author | Kim, Y.S. | - |
dc.contributor.author | Kim, D.W. | - |
dc.contributor.author | Park, S.H. | - |
dc.contributor.author | Jeong, J.H. | - |
dc.contributor.author | Kim, S.B. | - |
dc.contributor.author | Ha, D.W. | - |
dc.contributor.author | Park, J.H. | - |
dc.contributor.author | Rhee, H.S. | - |
dc.contributor.author | Hyun, S.J. | - |
dc.contributor.author | Shin, D.S. | - |
dc.contributor.author | Kim, D.H. | - |
dc.contributor.author | Kim, H.Y. | - |
dc.contributor.author | Maeda, S. | - |
dc.contributor.author | Lee, K.H. | - |
dc.contributor.author | Kim, M.C. | - |
dc.contributor.author | Koh, Y.S. | - |
dc.contributor.author | Yoon, B. | - |
dc.contributor.author | Shin, K. | - |
dc.contributor.author | Lee, N.I. | - |
dc.contributor.author | Kangh, S.B. | - |
dc.contributor.author | Hwang, K.H. | - |
dc.contributor.author | Lee, J.H. | - |
dc.contributor.author | Ku, J.-H. | - |
dc.contributor.author | Nam, S.W. | - |
dc.contributor.author | Jung, S.M. | - |
dc.contributor.author | Kang, H.K. | - |
dc.contributor.author | Yoon, J.S. | - |
dc.contributor.author | Jung, E.S. | - |
dc.date.accessioned | 2023-12-19T20:37:38Z | - |
dc.date.available | 2023-12-19T20:37:38Z | - |
dc.date.created | 2022-04-06 | - |
dc.date.issued | 2016-06-13 | - |
dc.description.abstract | 10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated. | - |
dc.identifier.bibliographicCitation | 36th IEEE Symposium on VLSI Technology | - |
dc.identifier.doi | 10.1109/VLSIT.2016.7573359 | - |
dc.identifier.issn | 0743-1562 | - |
dc.identifier.scopusid | 2-s2.0-84990879021 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/58525 | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications | - |
dc.type | Conference Paper | - |
dc.date.conferenceDate | 2016-06-13 | - |
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