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- Jeong, Changwook
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Impact of BTBT, stress and interface charge on optimum Ge in SiGe pMOS for low power applications
- Author(s)
- Dhar, S., Noh, H.K., Kim, S.J., Kim, H.W., Wu, Z., Lee, W.S., Bhuwalka, K.K., Kim, J.C., Jeong, Changwook, Kwon, U.H., Maeda, S., Lee, K.H., Pham, A.T., Jin, S., Choi, W.S.
- Issued Date
- 2016-10-20
- Citation
- 2016 International Conference on Simulation of Semiconductor Processes and Devices, pp.345 - 348
- Abstract
- The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (IEFF @ fixed IOFF) standpoint is evaluated, considering three key device aspects-stress, band-to-band-tunneling (BTBT), and interface charge density (DIT). The analysis reveals that while for high Ge (>90%), performance is limited by BTBT, overall stress reduction beyond Ge 65% further limits performance. Including realistic (DIT) profile further shows that optimum Ge content is between 40%∼50% for low power applications. © 2016 IEEE.
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
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