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DC Field | Value | Language |
---|---|---|
dc.citation.conferencePlace | GE | - |
dc.citation.conferencePlace | Nuremberg | - |
dc.citation.endPage | 348 | - |
dc.citation.startPage | 345 | - |
dc.citation.title | 2016 International Conference on Simulation of Semiconductor Processes and Devices | - |
dc.contributor.author | Dhar, S. | - |
dc.contributor.author | Noh, H.K. | - |
dc.contributor.author | Kim, S.J. | - |
dc.contributor.author | Kim, H.W. | - |
dc.contributor.author | Wu, Z. | - |
dc.contributor.author | Lee, W.S. | - |
dc.contributor.author | Bhuwalka, K.K. | - |
dc.contributor.author | Kim, J.C. | - |
dc.contributor.author | Jeong, Changwook | - |
dc.contributor.author | Kwon, U.H. | - |
dc.contributor.author | Maeda, S. | - |
dc.contributor.author | Lee, K.H. | - |
dc.contributor.author | Pham, A.T. | - |
dc.contributor.author | Jin, S. | - |
dc.contributor.author | Choi, W.S. | - |
dc.date.accessioned | 2023-12-19T20:06:26Z | - |
dc.date.available | 2023-12-19T20:06:26Z | - |
dc.date.created | 2022-04-06 | - |
dc.date.issued | 2016-10-20 | - |
dc.description.abstract | The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (IEFF @ fixed IOFF) standpoint is evaluated, considering three key device aspects-stress, band-to-band-tunneling (BTBT), and interface charge density (DIT). The analysis reveals that while for high Ge (>90%), performance is limited by BTBT, overall stress reduction beyond Ge 65% further limits performance. Including realistic (DIT) profile further shows that optimum Ge content is between 40%∼50% for low power applications. © 2016 IEEE. | - |
dc.identifier.bibliographicCitation | 2016 International Conference on Simulation of Semiconductor Processes and Devices, pp.345 - 348 | - |
dc.identifier.doi | 10.1109/SISPAD.2016.7605217 | - |
dc.identifier.scopusid | 2-s2.0-85015670763 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/58524 | - |
dc.language | 영어 | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Impact of BTBT, stress and interface charge on optimum Ge in SiGe pMOS for low power applications | - |
dc.type | Conference Paper | - |
dc.date.conferenceDate | 2016-09-06 | - |
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