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- Kim, Kyung Rok
- Nano-Electronic Emerging Devices Lab.
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Nanoscale Poly-Si Line Formation and Its Uniformity
- Author(s)
- Choi, Woo Young, Sung, Suk Kang, Kim, Kyung Rok, Lee, Jong Duk, Park, Byung-Gook
- Issued Date
- 2001-07-01
- Citation
- Asia-Pacific Workshop on Fundamental and application of Advanced Semiconductor Devices, pp.11 - 16
- Abstract
- A patterning technique to define nanoscale poly-Si lines is developed using sidewall structure. In this experiment, sidewall patterning technique makes it possible to realize 30nm, 50nm and 80nm poly-Si lines accurately, uniformly, and reproducibly. We have compared this technique with e-beam lithography. It is expected that the sidewall patterning technique can be applied to nanoscale MOSFET fabrication.
- Publisher
- IEEE Korea Chapter
- ISSN
- 0913-5685
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