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- Kim, Kyung Rok
- Nano-Electronic Emerging Devices Lab.
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.conferencePlace | KO | - |
| dc.citation.endPage | 16 | - |
| dc.citation.startPage | 11 | - |
| dc.citation.title | Asia-Pacific Workshop on Fundamental and application of Advanced Semiconductor Devices | - |
| dc.contributor.author | Choi, Woo Young | - |
| dc.contributor.author | Sung, Suk Kang | - |
| dc.contributor.author | Kim, Kyung Rok | - |
| dc.contributor.author | Lee, Jong Duk | - |
| dc.contributor.author | Park, Byung-Gook | - |
| dc.date.accessioned | 2023-12-20T06:35:56Z | - |
| dc.date.available | 2023-12-20T06:35:56Z | - |
| dc.date.created | 2014-12-23 | - |
| dc.date.issued | 2001-07-01 | - |
| dc.description.abstract | A patterning technique to define nanoscale poly-Si lines is developed using sidewall structure. In this experiment, sidewall patterning technique makes it possible to realize 30nm, 50nm and 80nm poly-Si lines accurately, uniformly, and reproducibly. We have compared this technique with e-beam lithography. It is expected that the sidewall patterning technique can be applied to nanoscale MOSFET fabrication. | - |
| dc.identifier.bibliographicCitation | Asia-Pacific Workshop on Fundamental and application of Advanced Semiconductor Devices, pp.11 - 16 | - |
| dc.identifier.issn | 0913-5685 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/52282 | - |
| dc.publisher | IEEE Korea Chapter | - |
| dc.title | Nanoscale Poly-Si Line Formation and Its Uniformity | - |
| dc.type | Conference Paper | - |
| dc.date.conferenceDate | 2001-07-01 | - |
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