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Kim, Kyung Rok
Nano-Electronic Emerging Devices Lab.
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Realistic Single-Electron Transistor Modeling and Novel CMOS/SET Hybrid Circuits

Author(s)
Kim, Kyung RokSong, Ki-WhanBaek, GwanghyeonLee, Sang-HoonKim, Dae HwanPark, Byung-GookWoo, Dong-SooSim, Jae SungLee, Jong Duk
Issued Date
2003-08-12
DOI
10.1109/NANO.2003.1231729
URI
https://scholarworks.unist.ac.kr/handle/201301/46891
Fulltext
https://ieeexplore.ieee.org/document/1231729
Citation
2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003, pp.119 - 121
Abstract
A practical single electron transistor (SET) model has been proposed with appropriate modifications to the previous analytical model. We have observed that non-ideal SET current behaviors such as turn-off and peak-to-valley ratio (PVCR) degradation is successfully reproduced by the new SET model. Based on the realistic SET model, we have developed a novel circuit scheme which enhances the stability of CMOS/SET hybrid logic. It is demonstrated that a universal literal gate with complementary self-biasing scheme operates quite well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation degrades severely.
Publisher
2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003
ISSN
1944-9399

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