Realistic Single-Electron Transistor Modeling and Novel CMOS/SET Hybrid Circuits

Abstract

A practical single electron transistor (SET) model has been proposed with appropriate modifications to the previous analytical model. We have observed that non-ideal SET current behaviors such as turn-off and peak-to-valley ratio (PVCR) degradation is successfully reproduced by the new SET model. Based on the realistic SET model, we have developed a novel circuit scheme which enhances the stability of CMOS/SET hybrid logic. It is demonstrated that a universal literal gate with complementary self-biasing scheme operates quite well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation degrades severely.