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Bien, Franklin
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A reconfigurable 0.18-mu m CMOS equalizer IC with an improved tunable delay-line for 10-Gb/sec backplane serial I/O links

Author(s)
Bien, FranklinKim, HyoungsooHur, YoungsikMaeng, MoonkyunGebara, EdwardLaskar, Joy
Issued Date
2006-06-11
DOI
10.1109/MWSYM.2006.249617
URI
https://scholarworks.unist.ac.kr/handle/201301/46876
Fulltext
https://ieeexplore.ieee.org/document/4014941
Citation
IEEE MTT-S International Microwave Symposium, pp.490 - 493
Abstract
In this paper, a reconfigurable CMOS equalizer is presented to accommodate vast variety of backplane channel loss characteristics. Backplane channels over different trace lengths and dielectric materials were measured and characterized. Feed-forward equalizer (FFE) topology with finite impulse response (FIR) architecture was chosen for optimal equalization for the corresponding backplane configurations. For a reconfigurable FFE IC implementation, wide-range tunable delay-line (15-ps ~ 74-ps) and variable tap-gain amplifier were fabricated in a 0.18-mum standard CMOS technology. The proposed reconfigurable FFE demonstrated successful equalization at 10Gb/sec over various channel configurations with 26mW power dissipation from a 1.8-V supply
Publisher
IEEE MTTS
ISSN
0149-645X

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