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- Bien, Franklin
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.conferencePlace | US | - |
| dc.citation.conferencePlace | San Francisco, CA | - |
| dc.citation.endPage | 493 | - |
| dc.citation.startPage | 490 | - |
| dc.citation.title | IEEE MTT-S International Microwave Symposium | - |
| dc.contributor.author | Bien, Franklin | - |
| dc.contributor.author | Kim, Hyoungsoo | - |
| dc.contributor.author | Hur, Youngsik | - |
| dc.contributor.author | Maeng, Moonkyun | - |
| dc.contributor.author | Gebara, Edward | - |
| dc.contributor.author | Laskar, Joy | - |
| dc.date.accessioned | 2023-12-20T05:08:47Z | - |
| dc.date.available | 2023-12-20T05:08:47Z | - |
| dc.date.created | 2014-12-23 | - |
| dc.date.issued | 2006-06-11 | - |
| dc.description.abstract | In this paper, a reconfigurable CMOS equalizer is presented to accommodate vast variety of backplane channel loss characteristics. Backplane channels over different trace lengths and dielectric materials were measured and characterized. Feed-forward equalizer (FFE) topology with finite impulse response (FIR) architecture was chosen for optimal equalization for the corresponding backplane configurations. For a reconfigurable FFE IC implementation, wide-range tunable delay-line (15-ps ~ 74-ps) and variable tap-gain amplifier were fabricated in a 0.18-mum standard CMOS technology. The proposed reconfigurable FFE demonstrated successful equalization at 10Gb/sec over various channel configurations with 26mW power dissipation from a 1.8-V supply | - |
| dc.identifier.bibliographicCitation | IEEE MTT-S International Microwave Symposium, pp.490 - 493 | - |
| dc.identifier.doi | 10.1109/MWSYM.2006.249617 | - |
| dc.identifier.issn | 0149-645X | - |
| dc.identifier.scopusid | 2-s2.0-34250368868 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/46876 | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/4014941 | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE MTTS | - |
| dc.title | A reconfigurable 0.18-mu m CMOS equalizer IC with an improved tunable delay-line for 10-Gb/sec backplane serial I/O links | - |
| dc.type | Conference Paper | - |
| dc.date.conferenceDate | 2006-06-11 | - |
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