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- Kim, Kyung Rok
- Nano-Electronic Emerging Devices Lab.
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.conferencePlace | US | - |
| dc.citation.conferencePlace | Hilton Hawaiian VillageHonolulu | - |
| dc.citation.title | Silicon Nanoelectronics Workshop, SNW 2014 | - |
| dc.contributor.author | Kim, Kyung Rok | - |
| dc.contributor.author | Shin, Sunhae | - |
| dc.contributor.author | Jang, Esan | - |
| dc.date.accessioned | 2023-12-20T00:06:09Z | - |
| dc.date.available | 2023-12-20T00:06:09Z | - |
| dc.date.created | 2015-07-01 | - |
| dc.date.issued | 2014-06-08 | - |
| dc.description.abstract | We propose a novel standard ternary inverter (STI) based on nanoscale planar CMOS technology for a compact design of multi-valued logic (MVL). By enhancing junction band-to-band tunneling (BTBT) leakage with high channel doping for STI operation, the 'third' intermediate state (VINT) can be successfully obtained at VDD/2 in the conventional binary CMOS inverter. It is demonstrated that the variability of the intermediate level (ΔVINT<80mV) can be allowable into the worst noise margin (>0.1V). | - |
| dc.identifier.bibliographicCitation | Silicon Nanoelectronics Workshop, SNW 2014 | - |
| dc.identifier.doi | 10.1109/SNW.2014.7348572 | - |
| dc.identifier.scopusid | 2-s2.0-84963929016 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/46736 | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/7348572 | - |
| dc.language | 영어 | - |
| dc.publisher | Silicon Nanoelectronics Workshop, SNW 2014 | - |
| dc.title | Standard Ternary Inverter Based on Junction Leakage-Enhanced Nanoscale Planar CMOS and Its Variation Immunity | - |
| dc.type | Conference Paper | - |
| dc.date.conferenceDate | 2014-06-08 | - |
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