dc.citation.conferencePlace |
US |
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dc.citation.conferencePlace |
Hilton Hawaiian VillageHonolulu |
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dc.citation.title |
Silicon Nanoelectronics Workshop, SNW 2014 |
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dc.contributor.author |
Kim, Kyung Rok |
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dc.contributor.author |
Shin, Sunhae |
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dc.date.accessioned |
2023-12-20T00:06:08Z |
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dc.date.available |
2023-12-20T00:06:08Z |
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dc.date.created |
2015-07-01 |
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dc.date.issued |
2014-06-09 |
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dc.description.abstract |
We propose a novel tri-state latch based on single-peak MOS-NDR. By shifting peak voltage over half of the supply voltage, tri-state memory can be implemented. The fully suppressed valley current of MOS-NDR guarantees the supply voltage design margin in tri-state logic and memory. |
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dc.identifier.bibliographicCitation |
Silicon Nanoelectronics Workshop, SNW 2014 |
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dc.identifier.doi |
10.1109/SNW.2014.7348610 |
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dc.identifier.scopusid |
2-s2.0-84963828701 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/46734 |
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dc.identifier.url |
https://ieeexplore.ieee.org/document/7348610 |
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dc.language |
영어 |
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dc.publisher |
Silicon Nanoelectronics Workshop, SNW 2014 |
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dc.title |
Novel Tri-State Latch using Single-Peak Negative Differential Resistance Devices |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2014-06-08 |
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