dc.citation.conferencePlace |
KO |
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dc.citation.conferencePlace |
Seoul |
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dc.citation.title |
ITC-CSCC 2015 |
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dc.contributor.author |
Kim, Kyung Rok |
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dc.contributor.author |
Shin, Sunhae |
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dc.contributor.author |
Jang, Esan |
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dc.contributor.author |
Jung, Jae Won |
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dc.date.accessioned |
2023-12-19T22:09:28Z |
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dc.date.available |
2023-12-19T22:09:28Z |
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dc.date.created |
2015-12-31 |
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dc.date.issued |
2015-07-02 |
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dc.description.abstract |
We propose a novel standard ternary inverter (STI) based on nanoscale planar CMOS technology for a compact design of multi-valued logic (MVL). By enhancing junction band-to-band tunneling (BTBT) leakage with high channel doping for STI operation, the “third” intermediate state (VINT) can be successfully obtained at VDD/2 in the conventional binary CMOS inverter. The junction BTBT off-leakage variation effects are investigated by considering doping fluctuation in the mixed-mode device simulation. It is demonstrated that the variability of the intermediate level (DVINT< 80 mV) can be allowable into the worst noise margin (> 0.1 V) of STI operation. |
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dc.identifier.bibliographicCitation |
ITC-CSCC 2015 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/42015 |
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dc.language |
영어 |
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dc.publisher |
IEIE, IEICE, The Electrical Engineering / Electronics, Computer, Telecommunications and Information Association |
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dc.title |
Multi-Valued Logic Based on CMOS technology |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2015-06-29 |
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