dc.citation.conferencePlace |
KO |
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dc.citation.conferencePlace |
jeju |
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dc.citation.endPage |
308 |
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dc.citation.startPage |
307 |
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dc.citation.title |
23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 |
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dc.contributor.author |
Lee, Yongsun |
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dc.contributor.author |
Seong, Taeho |
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dc.contributor.author |
Yoo, Seyeon |
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dc.contributor.author |
Choi, Jaehyouk |
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dc.date.accessioned |
2023-12-19T17:37:47Z |
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dc.date.available |
2023-12-19T17:37:47Z |
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dc.date.created |
2018-06-12 |
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dc.date.issued |
2018-01-22 |
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dc.description.abstract |
A low-jitter, low-reference spur switched-loop-filter (SLF) PLL that uses a fast phase-error correction (FPEC) technique emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM) is presented. Even for a high multiplication factor (i.e., 64), the proposed SLF PLL concurrently achieved ultra-low jitter and low reference spur. The prototype was fabricated in a 65-nm CMOS process. The RMS-jitter, the FOM, and the reference spur were measured as 378 fs, -242 dB, and -71 dBc, respectively. |
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dc.identifier.bibliographicCitation |
23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, pp.307 - 308 |
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dc.identifier.doi |
10.1109/ASPDAC.2018.8297333 |
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dc.identifier.isbn |
978-150900602-1 |
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dc.identifier.scopusid |
2-s2.0-85045313689 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/37254 |
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dc.identifier.url |
https://ieeexplore.ieee.org/document/8297333/ |
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dc.language |
영어 |
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dc.publisher |
IEEE |
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dc.title |
A switched-loop-filter PLL with fast phase-error correction technique |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2018-01-22 |
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