File Download

There are no files associated with this item.

  • Find it @ UNIST can give you direct access to the published full text of this article. (UNISTARs only)
Related Researcher

김재준

Kim, Jae Joon
Circuits & Systems Design Lab.
Read More

Views & Downloads

Detailed Information

Cited time in webofscience Cited time in scopus
Metadata Downloads

Ultra-Wideband Design Methodology of CMOS Phase-locked Loops and Voltage-controlled Oscillators

Author(s)
김재준
Issued Date
2012-02-16
URI
https://scholarworks.unist.ac.kr/handle/201301/36998
Citation
제19회 한국반도체학술대회
Abstract
A ultra-wideband architecture of RF phase-locked loops (PLL) is introduced, which might give very wide frequency range from 900MHz to 77GHz, covering most existing wireless standards. The basic architecture is based on a post-processing array composed of frequency dividers and multipliers, which is located after the PLL output. The prerequisite for its continuous frequency generation over the whole range is to implement a very wideband voltage-controlled oscillator (VCO) whose maximum frequency is at least twice greater than its minimum frequency. To verify the feasibility of this PLL architecture, a wideband VCO prototype was fabricated in a 65nm CMOS process, and verified to have the frequency range from 4.2GHz to 18.7GHz. Based on this achievement, further on-going studies on frequency multipliers are expected to expand current PLL frequency range up to the Terahertz frequency.
Publisher
한국반도체연구조합

qrcode

Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.