Ultra-Wideband Design Methodology of CMOS Phase-locked Loops and Voltage-controlled Oscillators

Abstract

A ultra-wideband architecture of RF phase-locked loops (PLL) is introduced, which might give very wide frequency range from 900MHz to 77GHz, covering most existing wireless standards. The basic architecture is based on a post-processing array composed of frequency dividers and multipliers, which is located after the PLL output. The prerequisite for its continuous frequency generation over the whole range is to implement a very wideband voltage-controlled oscillator (VCO) whose maximum frequency is at least twice greater than its minimum frequency. To verify the feasibility of this PLL architecture, a wideband VCO prototype was fabricated in a 65nm CMOS process, and verified to have the frequency range from 4.2GHz to 18.7GHz. Based on this achievement, further on-going studies on frequency multipliers are expected to expand current PLL frequency range up to the Terahertz frequency.