Transistor Layout Optimization for Leakage Saving

Abstract

In this paper, we investigate electrical effects of transistor layout shape (both in the channel and diffusion) on the performance and leakage current. Through layout optimization techniques, we propose a novel intra-gate biasing technique to reduce leakage current while maintaining drive current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits. Diffusion rounding is another interesting effect which happens due to the imperfect source and drain profile in the sub-wavelength lithography regime. TCAD analysis shows that diffusion rounding at the transistor source side can provide increased Ion with decreased Ioff because of the edge effect. The proposed diffusion-rounded CMOS shows as much as 10% improvement both in the on-current (driving) and the off-current (leakage)