dc.citation.conferencePlace |
RS |
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dc.citation.conferencePlace |
Novi Sad, Serbia |
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dc.citation.endPage |
289 |
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dc.citation.startPage |
284 |
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dc.citation.title |
IEEE International Symposium on Multiple-Valued Logic |
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dc.contributor.author |
Shin, Sunhae |
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dc.contributor.author |
Jang, Esan |
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dc.contributor.author |
Jeong, Jae Won |
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dc.contributor.author |
Kim, Kyung Rok |
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dc.date.accessioned |
2023-12-19T19:06:30Z |
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dc.date.available |
2023-12-19T19:06:30Z |
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dc.date.created |
2017-09-27 |
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dc.date.issued |
2017-05-22 |
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dc.description.abstract |
We propose the feasible and scalable ternary CMOS (T-CMOS) device platform for a fully CMOS-compatible physical synthesis of multi-valued logic (MVL) circuits. By developing the compact model of T-CMOS and verifying the physical model parameters with experimental data, the T-CMOS design framework based on standard ternary inverter (STI) is presented for static noise margin (SNM) enhancement and performance analysis of ternary logic gates. |
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dc.identifier.bibliographicCitation |
IEEE International Symposium on Multiple-Valued Logic, pp.284 - 289 |
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dc.identifier.doi |
10.1109/ISMVL.2017.48 |
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dc.identifier.issn |
2378-2226 |
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dc.identifier.scopusid |
2-s2.0-85026735191 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/32762 |
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dc.identifier.url |
http://ieeexplore.ieee.org/document/7965005/ |
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dc.language |
영어 |
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dc.publisher |
IEEE |
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dc.title |
CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2017-05-22 |
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