dc.citation.conferencePlace |
JA |
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dc.citation.conferencePlace |
Rihga Royal HotelKyoto |
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dc.citation.title |
IEEE Symposium on VLSI Circuits |
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dc.contributor.author |
Seong, Taeho |
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dc.contributor.author |
Lee, Yongsun |
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dc.contributor.author |
Yoo, Seyeon |
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dc.contributor.author |
Choi, Jaehyouk |
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dc.date.accessioned |
2023-12-19T18:41:27Z |
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dc.date.available |
2023-12-19T18:41:27Z |
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dc.date.created |
2017-06-09 |
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dc.date.issued |
2017-06-07 |
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dc.description.abstract |
This work presents an ultra-low jitter and low reference spur switched-loop-filter (SLF) PLL, using a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). Thus, despite a high multiplication factor (i.e., 64), the proposed SLF-PLL achieved ultra-low jitter and low reference spur, concurrently. From the prototype fabricated using a 65-nm CMOS process, the RMS-jitter, the FOM, and the reference spur were measured as 378 fs, −242 dB, and −71 dBc, respectively. |
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dc.identifier.bibliographicCitation |
IEEE Symposium on VLSI Circuits |
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dc.identifier.doi |
10.23919/VLSIC.2017.8008476 |
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dc.identifier.scopusid |
2-s2.0-85034031924 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/32760 |
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dc.identifier.url |
http://ieeexplore.ieee.org/document/8008476/ |
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dc.language |
영어 |
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dc.publisher |
IEEE |
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dc.title |
A -242-dB FOM and -71-dBc Reference Spur Ring-VCO-Based Ultra-Low Jitter Switched-Loop-Filter PLL Using Fast Phase-Error Correction Technique |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2017-06-05 |
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