Input polling arbitration mechanism for a gigabit packet switch
Cited 0 times inCited 0 times in
- Input polling arbitration mechanism for a gigabit packet switch
- Son, J.W.; Oh, Y.Y.; Lee, H.T.; Lee, Jaiyong; Lee, S.B.
- Issue Date
- Institution of Engineering and Technology
- Electronics Letters, v.32, no.22, pp.2050 - 2051
- Two head of line (HOL) packet arbitration mechanisms in an input buffered gigabit packet switch are proposed. These mechanisms have significant advantages in simple implementation while their performances still remain at acceptable levels.
- Appears in Collections:
- ECE_Journal Papers
- Files in This Item:
- There are no files associated with this item.
can give you direct access to the published full text of this article. (UNISTARs only)
Show full item record
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.