Input polling arbitration mechanism for a gigabit packet switch

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Title
Input polling arbitration mechanism for a gigabit packet switch
Author
Son, J.W.Oh, Y.Y.Lee, H.T.Lee, JaiyongLee, S.B.
Issue Date
1996-10
Publisher
Institution of Engineering and Technology
Citation
Electronics Letters, v.32, no.22, pp.2050 - 2051
Abstract
Two head of line (HOL) packet arbitration mechanisms in an input buffered gigabit packet switch are proposed. These mechanisms have significant advantages in simple implementation while their performances still remain at acceptable levels.
URI
https://scholarworks.unist.ac.kr/handle/201301/32138
URL
https://ieeexplore.ieee.org/document/543807?arnumber=543807&tag=1
DOI
10.1049/el:19961368
ISSN
0013-5194
Appears in Collections:
ECE_Journal Papers
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