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Lee, Jaiyong
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dc.citation.endPage 2051 -
dc.citation.number 22 -
dc.citation.startPage 2050 -
dc.citation.title Electronics Letters -
dc.citation.volume 32 -
dc.contributor.author Son, J.W. -
dc.contributor.author Oh, Y.Y. -
dc.contributor.author Lee, H.T. -
dc.contributor.author Lee, Jaiyong -
dc.contributor.author Lee, S.B. -
dc.date.accessioned 2023-12-22T12:38:43Z -
dc.date.available 2023-12-22T12:38:43Z -
dc.date.created 2020-05-14 -
dc.date.issued 1996-10 -
dc.description.abstract Two head of line (HOL) packet arbitration mechanisms in an input buffered gigabit packet switch are proposed. These mechanisms have significant advantages in simple implementation while their performances still remain at acceptable levels. -
dc.identifier.bibliographicCitation Electronics Letters, v.32, no.22, pp.2050 - 2051 -
dc.identifier.doi 10.1049/el:19961368 -
dc.identifier.issn 0013-5194 -
dc.identifier.scopusid 2-s2.0-0030262977 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/32138 -
dc.identifier.url https://ieeexplore.ieee.org/document/543807?arnumber=543807&tag=1 -
dc.language 영어 -
dc.publisher Institution of Engineering and Technology -
dc.title Input polling arbitration mechanism for a gigabit packet switch -
dc.type Article -
dc.description.isOpenAccess FALSE -
dc.type.docType Article -
dc.description.journalRegisteredClass scopus -
dc.subject.keywordAuthor Packet switching -
dc.subject.keywordAuthor Protocols -
dc.subject.keywordPlus Buffer circuits -
dc.subject.keywordPlus Crossbar equipment -
dc.subject.keywordPlus Data communication equipment -
dc.subject.keywordPlus Data communication systems -
dc.subject.keywordPlus Network protocols -
dc.subject.keywordPlus Packet switching -
dc.subject.keywordPlus Head of line (HOL) packet arbitration mechanisms -
dc.subject.keywordPlus Input polling arbitration (IPA) -
dc.subject.keywordPlus Packet networks -

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