CMOS Backplane Pixel Circuit with Leakage and Voltage Compensation for an Micro-LED Display achieving 5,000 PPI or higher

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Title
CMOS Backplane Pixel Circuit with Leakage and Voltage Compensation for an Micro-LED Display achieving 5,000 PPI or higher
Author
Seong, JewooJang, JinwoongLee, JaehoonLee, Myunghee
Issue Date
2020-03
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
IEEE ACCESS, v.8, pp.49467 - 49476
Abstract
Micro-displays based on micro-LEDs are becoming more and more attractive in AR/MR (Augmented/Mixed Reality) applications. A display size of 0.5 to 0.7-inch is preferred, with 5,000 PPI (Pixel Per Inch) or higher. Due to this pixel density and size, a CMOS (Complementary Metal-Oxide-Silicon) backplane is an ideal solution to drive these pixelized micro-LEDs. As the required pixel size gets smaller, the design of the appropriate pixel circuit becomes more challenging. The simplest 2T1C (2 transistors & 1 capacitor) pixel circuit has potential problems, due to the leakage current of the switch transistor and the voltage drop on the matrix array layout. In this paper, a pixel circuit is proposed as a solution to overcome these two issues. Our simulation results show that the variation of the driving current to the LED is improved by 95 %, and the IR drop error rate is around 2.2 % compared to the 2T1C circuit. The test results also show that the error rate of IPIXEL for the whole region of display is under 2.5 %. This work is verified using a test chip implementation with 180 nm CMOS process technology.
URI
https://scholarworks.unist.ac.kr/handle/201301/31545
URL
https://ieeexplore.ieee.org/document/9031408
DOI
10.1109/ACCESS.2020.2979883
ISSN
2169-3536
Appears in Collections:
ECE_Journal Papers
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