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A 0.1-1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC

Author(s)
Park, SuneuiKim, JuyeopHwang, ChanwoongPark, HangiYoo, SeyeonSeong, TaehoChoi, Jaehyouk
Issued Date
2019-08
DOI
10.1109/LMWC.2019.2921718
URI
https://scholarworks.unist.ac.kr/handle/201301/27486
Fulltext
https://ieeexplore.ieee.org/document/8744239
Citation
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.29, no.8, pp.548 - 550
Abstract
This letter presents a delay-locked loop (DLL) that can have a wide harmonic-locking-free frequency range, by using a digital-to-analog converter-based (DAC-based) band-selection circuit (BSC). The proposed exponential DAC (EDAC) used for the BSC generates a set of initial control voltages that follow a geometric sequence while satisfying the condition for avoiding harmonic locking. Thus, the BSC can cover a much wider range of frequencies free from harmonic locking than it could cover when it used a conventional, linear DAC that generated a set of control voltages following an arithmetic sequence. In this letter, the DLL was fabricated in a 65-nm CMOS and it had a measured harmonic-locking-free range from 0.1 to 1.5 GHz. The measured 1-MHz phase noise and rms jitter at 1.0 GHz were -128 dBc/Hz and 1.99 ps, respectively. The active area was 0.052 mm(2), and the power consumption was 5.5 mW.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
1531-1309
Keyword (Author)
Delay-locked loop (DLL)digital-to-analog converter (DAC)harmonic locking
Keyword
DLL

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