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정홍식

Jeong, Hongsik
Future Semiconductor Technology Lab.
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Enhanced write performance of a 64-Mb phase-change random access memory

Author(s)
Oh, Hyung-rokCho, Beak-hyungCho, Woo YeongKang, SangbeomChoi, Byung-gilKim, Hye-jinKim, Ki-sungKim, Du-eungKwak, Choong-keunByun, Hyun-geunJeong, Gi-taeJeong, Hong-sikKim, Kinam
Issued Date
2006-01
DOI
10.1109/JSSC.2005.859016
URI
https://scholarworks.unist.ac.kr/handle/201301/27159
Fulltext
https://ieeexplore.ieee.org/document/1564352
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.41, no.1, pp.122 - 126
Abstract
The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-mu m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
0018-9200
Keyword (Author)
distributionphase changePRAMRESETset

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