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- Jeong, Hongsik
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.endPage | 126 | - |
| dc.citation.number | 1 | - |
| dc.citation.startPage | 122 | - |
| dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
| dc.citation.volume | 41 | - |
| dc.contributor.author | Oh, Hyung-rok | - |
| dc.contributor.author | Cho, Beak-hyung | - |
| dc.contributor.author | Cho, Woo Yeong | - |
| dc.contributor.author | Kang, Sangbeom | - |
| dc.contributor.author | Choi, Byung-gil | - |
| dc.contributor.author | Kim, Hye-jin | - |
| dc.contributor.author | Kim, Ki-sung | - |
| dc.contributor.author | Kim, Du-eung | - |
| dc.contributor.author | Kwak, Choong-keun | - |
| dc.contributor.author | Byun, Hyun-geun | - |
| dc.contributor.author | Jeong, Gi-tae | - |
| dc.contributor.author | Jeong, Hong-sik | - |
| dc.contributor.author | Kim, Kinam | - |
| dc.date.accessioned | 2023-12-22T10:08:43Z | - |
| dc.date.available | 2023-12-22T10:08:43Z | - |
| dc.date.created | 2019-07-11 | - |
| dc.date.issued | 2006-01 | - |
| dc.description.abstract | The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-mu m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively. | - |
| dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.41, no.1, pp.122 - 126 | - |
| dc.identifier.doi | 10.1109/JSSC.2005.859016 | - |
| dc.identifier.issn | 0018-9200 | - |
| dc.identifier.scopusid | 2-s2.0-31344479086 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/27159 | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/1564352 | - |
| dc.identifier.wosid | 000234305600014 | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
| dc.title | Enhanced write performance of a 64-Mb phase-change random access memory | - |
| dc.type | Article | - |
| dc.description.isOpenAccess | FALSE | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.type.docType | Article; Proceedings Paper | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordAuthor | distribution | - |
| dc.subject.keywordAuthor | phase change | - |
| dc.subject.keywordAuthor | PRAM | - |
| dc.subject.keywordAuthor | RESET | - |
| dc.subject.keywordAuthor | set | - |
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