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- Jeong, Hongsik
- Future Semiconductor Technology Lab.
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A 0.18-mu m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)
- Author(s)
- Cho, Woo Yeong, Cho, Beak-Hyung, Choi, Byung-Gil, Oh, Hyung-Rok, Kang, Sangbeom, Kim, Ki-Sung, Kim, Kyung-Hee, Kim, Du-Eung, Kwak, Choong-Keun, Byun, Hyun-Geun, Hwang, Youngnam, Ahn, S., Koh, Gwan-Hyeob, Jeong, Gitae, Jeong, Hongsik, Kim, Kinam
- Issued Date
- 2005-01
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.40, no.1, pp.293 - 300
- Abstract
- A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge2Sb2Te5) into 0.18-mum CMOS technology. To optimize SET/RESET distribution, 512-kb sub-array core architecture was proposed, featuring meshed ground line and separated SET/RESET control schemes. Random read access time, random SET and RESET write access times were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V supply voltage with 30degreesC.
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- ISSN
- 0018-9200
- Keyword (Author)
- phase change, phase-transition random access memory (PRAM), RESET, SET
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