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- Jeong, Hongsik
- Future Semiconductor Technology Lab.
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.endPage | 300 | - |
| dc.citation.number | 1 | - |
| dc.citation.startPage | 293 | - |
| dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
| dc.citation.volume | 40 | - |
| dc.contributor.author | Cho, Woo Yeong | - |
| dc.contributor.author | Cho, Beak-Hyung | - |
| dc.contributor.author | Choi, Byung-Gil | - |
| dc.contributor.author | Oh, Hyung-Rok | - |
| dc.contributor.author | Kang, Sangbeom | - |
| dc.contributor.author | Kim, Ki-Sung | - |
| dc.contributor.author | Kim, Kyung-Hee | - |
| dc.contributor.author | Kim, Du-Eung | - |
| dc.contributor.author | Kwak, Choong-Keun | - |
| dc.contributor.author | Byun, Hyun-Geun | - |
| dc.contributor.author | Hwang, Youngnam | - |
| dc.contributor.author | Ahn, S. | - |
| dc.contributor.author | Koh, Gwan-Hyeob | - |
| dc.contributor.author | Jeong, Gitae | - |
| dc.contributor.author | Jeong, Hongsik | - |
| dc.contributor.author | Kim, Kinam | - |
| dc.date.accessioned | 2023-12-22T10:38:55Z | - |
| dc.date.available | 2023-12-22T10:38:55Z | - |
| dc.date.created | 2019-07-11 | - |
| dc.date.issued | 2005-01 | - |
| dc.description.abstract | A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge2Sb2Te5) into 0.18-mum CMOS technology. To optimize SET/RESET distribution, 512-kb sub-array core architecture was proposed, featuring meshed ground line and separated SET/RESET control schemes. Random read access time, random SET and RESET write access times were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V supply voltage with 30degreesC. | - |
| dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.40, no.1, pp.293 - 300 | - |
| dc.identifier.doi | 10.1109/JSSC.2004.837974 | - |
| dc.identifier.issn | 0018-9200 | - |
| dc.identifier.scopusid | 2-s2.0-19944427829 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/27114 | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/1375013 | - |
| dc.identifier.wosid | 000226124500030 | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
| dc.title | A 0.18-mu m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM) | - |
| dc.type | Article | - |
| dc.description.isOpenAccess | FALSE | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.type.docType | Article; Proceedings Paper | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordAuthor | phase change | - |
| dc.subject.keywordAuthor | phase-transition random access memory (PRAM) | - |
| dc.subject.keywordAuthor | RESET | - |
| dc.subject.keywordAuthor | SET | - |
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