Novel borderless metal contact process using a self-stopping layer for a 4Gb DRAM and beyond

Abstract

As the density of a DRAM increases to the giga-bit scale, the height of the cell capacitor node is increased more than 1 mum. As a result, the depth of the metal contact on the active area is increased more than 2 mum. For a 4-giga-bit DRAM with a 0.10 gm minimum feature size, the depth of the metal contact on the active area is more than 3 mum, due to the increased capacitor height and planarized inter-layer-dielectric layer, which is the critical etch depth for a reliable process margin. Also. the landing pad scheme for the metal contact cannot be applied to a DRAM with a 0.10 mum minimum feature size and beyond due to the lack of a space margin between the landing pad and neighboring bit-lines. To solve these issues. we developed a novel borderless metal contact process using self-stopping layer in 4-giga-bit DRAM with good contact resistance.