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Kim, Youngmin
Nano-scale(system) Design & Automation Lab
Research Interests
  • Design & Technology Co-Optimization (DTCO)

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A novel methodology for speeding up IC performance in 32nm FinFET

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Title
A novel methodology for speeding up IC performance in 32nm FinFET
Author
Nguyen, Hung VietRyu, MyunghwanKim, Youngmin
Keywords
Circuit designers; Double gate; FinFET; High performance; High-speed; IC designs; Low Power; Novel methodology; Signal propagation
Issue Date
2012-02
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v.9, no.4, pp.227 - 233
Abstract
This paper presents a novel methodology for IC speed-up in 32nm FinFET. By taking advantage of independently controlling two gates of IG-FinFET, we develop the boosting structures that can improve the signal propagation on interconnect significantly. Furthermore, the circuit area and power dissipation issues are also taken into account. With the addition of boosting path, the full booster can reduce the delay of interconnect as much as 50% while consuming merely more than 18% of power. In the high-speed and low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between the power consumption and high performance which play an important role in application-specific integration circuits in the 22nm node and beyond.
URI
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DOI
10.1587/elex.9.227
ISSN
1349-2543
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ECE_Journal Papers
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