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Kim, Youngmin
Nano-scale(system) Design & Automation Lab
Research Interests
  • Design & Technology Co-Optimization (DTCO)

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A high resolution and high linearity 45 nm CMOS fully digital voltage sensor for low power applications

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Title
A high resolution and high linearity 45 nm CMOS fully digital voltage sensor for low power applications
Author
Ryu, MyunghwanKim, Youngmin
Issue Date
2013-05
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v.10, no.13, pp.1 - 9
Abstract
This paper proposes a design of voltage sensor with new controllable delay element (CDE) having high linearity and high resolution. The proposed CDE uses power supply node to measure the voltage value. However, the delay increases exponentially at low voltage level. In this paper we add a PMOS header in parallel with the conventional CDE to compensate the delay degradation at lower voltage. We develop a 16-levels fully digital voltage sensor with a voltage range of 0.8 ~ 1.1V and 20mV resolution by using of the proposed delay elements. The proposed circuit is designed and simulated in a 45nm CMOS process. The simulation results show the feasibility of the high resolution and high linearity at low voltage by using of the proposed delay elements.
URI
https://scholarworks.unist.ac.kr/handle/201301/2532
URL
https://www.jstage.jst.go.jp/article/elex/10/13/10_10.20130400/_article
DOI
10.1587/elex.10.20130400
ISSN
1349-2543
Appears in Collections:
ECE_Journal Papers
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