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- Kim, Kyung Rok
- Nano-Electronic Emerging Devices Lab.
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.endPage | 1951 | - |
| dc.citation.number | 12 | - |
| dc.citation.startPage | 1948 | - |
| dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
| dc.citation.volume | 39 | - |
| dc.contributor.author | Heo, Sunwoo | - |
| dc.contributor.author | Kim, Sunmean | - |
| dc.contributor.author | Kim, Kiyung | - |
| dc.contributor.author | Lee, Hyeji | - |
| dc.contributor.author | Kim, So-Young | - |
| dc.contributor.author | Kim, Yun Ji | - |
| dc.contributor.author | Kim, Seong Mo | - |
| dc.contributor.author | Lee, Ho-In | - |
| dc.contributor.author | Lee, Segi | - |
| dc.contributor.author | Kim, Kyung Rok | - |
| dc.contributor.author | Kang, Seokhyeong | - |
| dc.contributor.author | Lee, Byoung Hun | - |
| dc.date.accessioned | 2023-12-21T20:09:49Z | - |
| dc.date.available | 2023-12-21T20:09:49Z | - |
| dc.date.created | 2018-10-15 | - |
| dc.date.issued | 2018-10 | - |
| dc.description.abstract | Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10-16 J, which is comparable with the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors. | - |
| dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.39, no.12, pp.1948 - 1951 | - |
| dc.identifier.doi | 10.1109/LED.2018.2874055 | - |
| dc.identifier.issn | 0741-3106 | - |
| dc.identifier.scopusid | 2-s2.0-85054505467 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/25020 | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/8482320 | - |
| dc.identifier.wosid | 000451587200031 | - |
| dc.language | 영어 | - |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
| dc.title | Ternary full adder using multi-threshold voltage graphene barristors | - |
| dc.type | Article | - |
| dc.description.isOpenAccess | TRUE | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordAuthor | Graphene barristor | - |
| dc.subject.keywordAuthor | ternary full adder | - |
| dc.subject.keywordAuthor | multi threshold voltage ternary graphene barristor | - |
| dc.subject.keywordAuthor | ternary logic | - |
| dc.subject.keywordPlus | FIELD-EFFECT TRANSISTOR | - |
| dc.subject.keywordPlus | DEVICE | - |
| dc.subject.keywordPlus | DESIGN | - |
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