A 4:1 Time Division Multiplexer(MUX) had been designed in using GaAs Cource Coupled FET Logic (SCFL). Designed Multiplexer uses a time devision frequency divider and two storage of signal combining 2:1 multiplexer. The performance of the multiplexer is verified by PSPICE simulation. Designed circuit operates up to 12.5 Gbit/s with a power dissipation of 192mW. These performance are more advanced than other reported multiplexer in the speed and power dissipation.