dc.citation.endPage |
154 |
- |
dc.citation.number |
2 |
- |
dc.citation.startPage |
147 |
- |
dc.citation.title |
한국통신학회논문지 |
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dc.citation.volume |
15 |
- |
dc.contributor.author |
김학선 |
- |
dc.contributor.author |
최병하 |
- |
dc.contributor.author |
이형재 |
- |
dc.date.accessioned |
2023-12-22T13:09:31Z |
- |
dc.date.available |
2023-12-22T13:09:31Z |
- |
dc.date.created |
2017-03-14 |
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dc.date.issued |
1990-02 |
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dc.description.abstract |
A 4:1 Time Division Multiplexer(MUX) had been designed in using GaAs Cource Coupled FET Logic (SCFL). Designed Multiplexer uses a time devision frequency divider and two storage of signal combining 2:1 multiplexer. The performance of the multiplexer is verified by PSPICE simulation. Designed circuit operates up to 12.5 Gbit/s with a power dissipation of 192mW. These performance are more advanced than other reported multiplexer in the speed and power dissipation. |
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dc.identifier.bibliographicCitation |
한국통신학회논문지, v.15, no.2, pp.147 - 154 |
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dc.identifier.issn |
1226-4717 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/21639 |
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dc.identifier.url |
http://www.dbpia.co.kr/Journal/ArticleDetail/NODE00211619 |
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dc.language |
영어 |
- |
dc.publisher |
한국통신학회 |
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dc.title.alternative |
기가주파수대 멀티플렉서 설계에 관한 연구 |
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dc.title |
Study of the Multigigabit Multiplexer Design |
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dc.type |
Article |
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dc.description.journalRegisteredClass |
other |
- |