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장지원

Chang, Jiwon
Exploratory Device Research Lab.
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Analytical Model of Short-Channel Double-Gate JFETs

Author(s)
Chang, JiwonKapoor, Ashok K.Register, Leonard F.Banerjee, Sanjay K.
Issued Date
2010-08
DOI
10.1109/TED.2010.2051193
URI
https://scholarworks.unist.ac.kr/handle/201301/21328
Fulltext
http://ieeexplore.ieee.org/document/5497123/
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v.57, no.8, pp.1846 - 1855
Abstract
In this paper, we propose a compact model of the short-channel double-gate (DG) JFETs, which are devices intended for low-power logic applications. In order to make the current equation continuous through all operating conditions from the subthreshold to well above the threshold without nonphysical fitting parameters, mobile carriers in depletion regions are considered. For describing the short-channel behavior, relevant parameters extracted from the 2-D analytical solution of Poisson's equation are used to modify long-channel equations. The field-dependent mobility, velocity saturation, channel-length modulation, and drain-induced barrier lowering are considered in the short-channel analysis. Models for the DG JFET are verified through numerically simulated current-voltage characteristics. Based on the model of the DG JFETs, the advantages of the DG JFETs over single-gate MOSFETs-which may have similar fabrication requirements-with the subthreshold regime are addressed.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
0018-9383

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