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High-Performance Plasmonic THz Detector Based on Asymmetric FET with Vertically Integrated Antenna in CMOS Technology

Author(s)
Ryu, Min WooLee, Jeong SeopKim, Kwan SungPark, KibogYang, Jong-RyulHan, Seong-TaeKim, Kyung Rok
Issued Date
2016-04
DOI
10.1109/TED.2016.2526677
URI
https://scholarworks.unist.ac.kr/handle/201301/18072
Fulltext
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=7412728
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v.63, no.4, pp.1742 - 1748
Abstract
We report a high-performance plasmonic terahertz (THz) detector based on antenna-coupled asymmetric field-effect transistor (FET) structure using 65-nm CMOS technology. By designing asymmetric FET on a self-aligned poly-Si gate structure, more enhanced channel charge asymmetry between source and drain has been obtained in comparison with non-self-aligned metal gate structure of our previous work. In addition, using vertically-integrated patch antenna, which is designed for 0.2 THz resonance frequency, we demonstrated the highly enhanced detection performance with responsivity (Rv) of 1.5 kV/W and noise-equivalent-power (NEP) of 15 pW/Hz0.5 at 0.2 THz.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN
0018-9383
Keyword (Author)
Asymmetric FETCMOSnoise-equivalent power (NEP)plasmonic terahertz (THz) detectorresponsivityself-aligned
Keyword
FOCAL-PLANE ARRAYTERAHERTZ RADIATIONSUB-TERAHERTZ

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