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Lee, Myunghee
Automotive Electronic Systems and Semiconductor Lab
Research Interests
  • Automotive Electronic System Design
  • Automtoive Semicondutor IC design

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A 3-DIMENSIONAL HIGH-THROUGHPUT ARCHITECTURE USING THROUGH-WAFER OPTICAL INTERCONNECT

Cited 16 times inthomson ciCited 14 times inthomson ci
Title
A 3-DIMENSIONAL HIGH-THROUGHPUT ARCHITECTURE USING THROUGH-WAFER OPTICAL INTERCONNECT
Author
WILLS, D. ScottLacy, W. StephenCamperi-Ginestet, ChristopheBuchanan, BrentCat, Huy H.Wilkinson, ScottLee, MyungheeJokerst, Nan MarieBrooke, Martin A.
Keywords
Amplifiers (electronic); Computer architecture; Digital circuits; Image processing; Integrated circuits; Interfaces (computer); Optoelectronic devices; Parallel processing systems; Silicon wafers; Thin films; Three dimensional; Topology
Issue Date
1995-06
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
JOURNAL OF LIGHTWAVE TECHNOLOGY, v.13, no.6, pp.1085 - 1092
Abstract
This paper presents a three-dimensional, highly parallel, optically interconnected system to process high-throughput stream data such as images, The vertical optical interconnections are realized using integrated optoelectronic devices operating at wavelengths to which silicon is transparent. These through-wafer optical signals are used to vertically optically interconnect stacked silicon circuits, The thin film optoelectronic devices are bonded directly to the stacked layers of silicon circuitry to realize self-contained vertical optical interconnections. Each integrated circuit layer contains analog interface circuitry, namely, detector amplifier and emitter driver circuitry, and digital circuitry for the network and/or processor, all of which are fabricated using a standard silicon integrated circuit foundry, These silicon circuits are post processed to integrate the thin him optoelectronics using standard, low cost, high yield microfabrication techniques. The three-dimensionally integrated architectures described herein are a network and a processor. The network has been designed to meet off-chip I/O using a new offset cube topology coupled with naming and routing schemes, The performance of this network is comparable to that of a three-dimensional mesh, The processing architecture has been defined to minimize overhead for basic parallel operations, The system goal for this research is to develop an integrated processing node for high-throughput, low-memory applications
URI
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DOI
10.1109/50.390224
ISSN
0733-8724
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