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DC Field | Value | Language |
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dc.citation.endPage | 1092 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 1085 | - |
dc.citation.title | JOURNAL OF LIGHTWAVE TECHNOLOGY | - |
dc.citation.volume | 13 | - |
dc.contributor.author | WILLS, D. Scott | - |
dc.contributor.author | Lacy, W. Stephen | - |
dc.contributor.author | Camperi-Ginestet, Christophe | - |
dc.contributor.author | Buchanan, Brent | - |
dc.contributor.author | Cat, Huy H. | - |
dc.contributor.author | Wilkinson, Scott | - |
dc.contributor.author | Lee, Myunghee | - |
dc.contributor.author | Jokerst, Nan Marie | - |
dc.contributor.author | Brooke, Martin A. | - |
dc.date.accessioned | 2023-12-22T12:41:51Z | - |
dc.date.available | 2023-12-22T12:41:51Z | - |
dc.date.created | 2015-07-23 | - |
dc.date.issued | 1995-06 | - |
dc.description.abstract | This paper presents a three-dimensional, highly parallel, optically interconnected system to process high-throughput stream data such as images, The vertical optical interconnections are realized using integrated optoelectronic devices operating at wavelengths to which silicon is transparent. These through-wafer optical signals are used to vertically optically interconnect stacked silicon circuits, The thin film optoelectronic devices are bonded directly to the stacked layers of silicon circuitry to realize self-contained vertical optical interconnections. Each integrated circuit layer contains analog interface circuitry, namely, detector amplifier and emitter driver circuitry, and digital circuitry for the network and/or processor, all of which are fabricated using a standard silicon integrated circuit foundry, These silicon circuits are post processed to integrate the thin him optoelectronics using standard, low cost, high yield microfabrication techniques. The three-dimensionally integrated architectures described herein are a network and a processor. The network has been designed to meet off-chip I/O using a new offset cube topology coupled with naming and routing schemes, The performance of this network is comparable to that of a three-dimensional mesh, The processing architecture has been defined to minimize overhead for basic parallel operations, The system goal for this research is to develop an integrated processing node for high-throughput, low-memory applications | - |
dc.identifier.bibliographicCitation | JOURNAL OF LIGHTWAVE TECHNOLOGY, v.13, no.6, pp.1085 - 1092 | - |
dc.identifier.doi | 10.1109/50.390224 | - |
dc.identifier.issn | 0733-8724 | - |
dc.identifier.scopusid | 2-s2.0-0029326183 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/12606 | - |
dc.identifier.url | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=390224 | - |
dc.identifier.wosid | A1995RE00200010 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 3-DIMENSIONAL HIGH-THROUGHPUT ARCHITECTURE USING THROUGH-WAFER OPTICAL INTERCONNECT | - |
dc.type | Article | - |
dc.description.journalRegisteredClass | scopus | - |
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