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Kang, Seokhyeong
System-on-Chip Design Lab
Research Interests
  • System-on-Chip, low power, computer-aided design, physical implementation

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Many-Core Token-Based Adaptive Power Gating

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dc.contributor.author Kahng, Andrew B. ko
dc.contributor.author Kang, Seokhyeong ko
dc.contributor.author Rosing, Tajana Simunic ko
dc.contributor.author Strong, Richard ko
dc.date.available 2015-07-03T06:40:42Z -
dc.date.created 2015-07-03 ko
dc.date.issued 2013-08 -
dc.identifier.citation IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.32, no.8, pp.1288 - 1292 ko
dc.identifier.issn 0278-0070 ko
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/11884 -
dc.identifier.uri http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6559076 ko
dc.description.abstract Among power dissipation components, leakage power has become more dominant with each successive technology node. Leakage energy waste can be reduced by power gating. In this paper, we extend token-based adaptive power gating (TAP), a technique to power gate an actively executing core during memory accesses, to many-core Chip Multi-Processors (CMPs). TAP works by tracking every system memory request and its estimated time of arrival so that a core may power gate itself without performance or energy loss. Previous work on TAP [11] shows several benefits compared to earlier state-of-the-art techniques [10], including zero performance hit and 2.58 times average energy savings for out-of-order cores. We show that TAP can adapt to increasing memory contention by increasing power-gated time by 3.69 times compared to a low memory-pressure case. We also scale TAP to many-core architectures with a distributed wake-up controller that is capable of supporting staggered wake-ups and able to power gate each core for 99.07% of the time, achieved by a non-scalable centralized scheme ko
dc.description.statementofresponsibility close -
dc.language ENG ko
dc.publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC ko
dc.subject Adaptive power gating ko
dc.subject energy savings ko
dc.subject low power design ko
dc.subject many-core architecture ko
dc.title Many-Core Token-Based Adaptive Power Gating ko
dc.type ARTICLE ko
dc.identifier.scopusid 2-s2.0-84880875139 ko
dc.identifier.wosid 000322026200013 ko
dc.type.rims ART ko
dc.description.wostc 1 *
dc.description.scopustc 2 *
dc.date.tcdate 2015-12-28 *
dc.date.scptcdate 2015-11-04 *
dc.identifier.doi 10.1109/TCAD.2013.2257923 ko
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