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DC Field | Value | Language |
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dc.citation.endPage | 1292 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1288 | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.citation.volume | 32 | - |
dc.contributor.author | Kahng, Andrew B. | - |
dc.contributor.author | Kang, Seokhyeong | - |
dc.contributor.author | Rosing, Tajana Simunic | - |
dc.contributor.author | Strong, Richard | - |
dc.date.accessioned | 2023-12-22T03:39:24Z | - |
dc.date.available | 2023-12-22T03:39:24Z | - |
dc.date.created | 2015-07-03 | - |
dc.date.issued | 2013-08 | - |
dc.description.abstract | Among power dissipation components, leakage power has become more dominant with each successive technology node. Leakage energy waste can be reduced by power gating. In this paper, we extend token-based adaptive power gating (TAP), a technique to power gate an actively executing core during memory accesses, to many-core Chip Multi-Processors (CMPs). TAP works by tracking every system memory request and its estimated time of arrival so that a core may power gate itself without performance or energy loss. Previous work on TAP [11] shows several benefits compared to earlier state-of-the-art techniques [10], including zero performance hit and 2.58 times average energy savings for out-of-order cores. We show that TAP can adapt to increasing memory contention by increasing power-gated time by 3.69 times compared to a low memory-pressure case. We also scale TAP to many-core architectures with a distributed wake-up controller that is capable of supporting staggered wake-ups and able to power gate each core for 99.07% of the time, achieved by a non-scalable centralized scheme | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.32, no.8, pp.1288 - 1292 | - |
dc.identifier.doi | 10.1109/TCAD.2013.2257923 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.scopusid | 2-s2.0-84880875139 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/11884 | - |
dc.identifier.url | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6559076 | - |
dc.identifier.wosid | 000322026200013 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Many-Core Token-Based Adaptive Power Gating | - |
dc.type | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Adaptive power gating | - |
dc.subject.keywordAuthor | energy savings | - |
dc.subject.keywordAuthor | low power design | - |
dc.subject.keywordAuthor | many-core architecture | - |
dc.subject.keywordPlus | LEAKAGE REDUCTION | - |
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