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A 10-Gb/s reconfigurable CMOS equalizer employing a transition detector-based output monitoring technique for band-limited serial links File

Bien, Franklin , Kim, Hyoungsoo , Hur, Youngsik , Maeng, Moonkyun , Cha, Jeongwon , Chandramouli, Soumya , Gebara, Edward , Laskar, Joy

Article Issue Date2006-12 View73
A novel clock recovery scheme with improved jitter tolerance for PAM4 signaling File

Kim, Hyoungsoo , Hur, Youngsik , Maeng, Moonkyun , Bien, Franklin , Chandramouli, S. , Gebara, Edward , Laskar, Joy

Conference Paper Issue Date2005-07-20 View48
A reconfigurable 0.18-mu m CMOS equalizer IC with an improved tunable delay-line for 10-Gb/sec backplane serial I/O links File

Bien, Franklin , Kim, Hyoungsoo , Hur, Youngsik , Maeng, Moonkyun , Gebara, Edward , Laskar, Joy

Conference Paper Issue Date2006-06-11 View39
A reconfigurable fully-integrated 0. 18-mu m CMOS feed-forward equalizer IC for 10-Gb/sec backplane links

Bien, Franklin , Hur, Youngsik , Maeng, Moonkyun , Kim, Hyoungsoo , Gebara, Edward , Laskar, Joy

Conference Paper Issue Date2006-05-21 View80
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